Conference Publications


[ 1] Arvind K. Karandikar, Peichen Pan, and C. L. Liu. Optimal Clock Period Clustering for Sequential Circuits with Retiming. In Proceedings of the IEEE International Conference on Computer Design, pages 122-127, 1997.

[ 2] Shrirang K. Karandikar and Sachin S. Sapatnekar. Technology Mapping for SOI Domino Logic Incorporating Solutions for the Parasitic Bipolar Effect. In Proceedings of the IEEE/ACM Design Automation Conference, pages 377-382, 2001.

[ 3] Shrirang K. Karandikar and Sachin S. Sapatnekar. Fast Comparisons of Circuit Implementations. In Proceedings of the Design, Automation and Test in Europe Conference, pages 910-915, 2004.

[ 4] Shrirang K. Karandikar and Sachin S. Sapatnekar. Logical Effort Based Technology Mapping. In Proceedings of the IEEE/ACM International Conference on Computer Aided Design, pages 419-422, 2004.

[ 5] Shrirang K. Karandikar and Sachin S. Sapatnekar. Fast Estimation Of Area-Delay Tradeoffs In Circuit Sizing. In Proceedings of the IEEE International Symposium on Circuits And Systems, pages 3575--3578, 2005.

[ 6] Shiyan Hu, Charles J. Alpert, Jiang Hu, Shrirang K. Karandikar, Zhuo Li, Weiping Shi and C.-N. Sze. Fast Algorithms for Slew Constrained Minimum Cost Buffering. In Proceedings of the IEEE/ACM Design Automation Conference, pages 308--313 2006.

[ 7] Shrirang K. Karandikar, Charles J. Alpert, Mehmet C. Yildiz, Paul Villarrubia, Stephen T. Quay, Tuhin Mahmud. Fast Electrical Correction Using Resizing and Buffering. In Proceedings of the IEEE/ACM Asia-South Pacific Design Automation Conference, pages 553--558,2007.

[ 8] Charles J. Alpert, Shrirang K. Karandikar, Zhuo Li, Gi-Joon Nam, Stephen T. Quay, Haoxing Ren, Cliff Sze, Paul Villarrubia, Mehmet C. Yildiz. The Nuts and Bolts of Physical Synthesis. In Proceedings of the 2007 International Workshop on System Level Interconnect Prediction, pages 89--94,2007.

[ 9] A. K. Agrawal, C. Bhattacharya, Prakalp Somawanshi, Mahesh Khadtare and Shrirang K. Karandikar Accelerated SAR Image Generation on GPGPU. In Proceedings of the 3rd Asia-Pacific Conference on Synthetic Aperture Radar , pages 371--374, 2011.

[10] Varad R. Deshmukh and Nishchay S. Mhatre and Shrirang K. Karandikar FIRA - A Novel Method for Benchmarking the Cache Hierarchy. In Proceedings of ACM COMPUTE 2012 , pages --,2012.

Journal Publications


[1] Peichen Pan, Arvind K. Karandikar, and C. L. Liu. Optimal Clock Period Clustering for Sequential Circuits with Retiming. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 17(6):489-498, June 1998.

[2] Shrirang K. Karandikar and Sachin S. Sapatnekar. Technology Mapping for SOI Domino Logic Incorporating Solutions for the Parasitic Bipolar Effect. IEEE Transactions on VLSI Systems, 11(6):1094-1105, December 2003.
Also see Erratum. IEEE Transactions on VLSI Systems, 12(6):669-670, June 2004.

[3] Shrirang K. Karandikar and Sachin S. Sapatnekar. Fast Comparisons of Circuit Implementations. IEEE Transactions on VLSI Systems, 13(12):1329--1339, December 2005.

[4] Charles J. Alpert, Shrirang K. Karandikar, Zhuo Li, Gi-Joon Nam, Stephen T. Quay, Haoxing Ren, C.-N. Sze, Paul G. Villarrubia and Mehmet Yildiz. Techniques for Fast Physical Synthesis. Proceedings of the IEEE, 95(3):573--579, March 2007.

[5] Shiyan Hu, Charles J. Alpert, Jiang Hu, Shrirang K. Karandikar, Zhuo Li, Weiping Shi and Chin-Ngai Sze. Fast Algorithms For Slew Constrained Minimum Cost Buffering. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 26(11):2009--2022, November 2007.

[6] Shrirang K. Karandikar and Sachin S. Sapatnekar. Technology Mapping Using Logical Effort Solving the Load Distribution Problem. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 27(1):45--58, January 2008.

Invited Talks, Presentations and Workshops without proceedings


[ 1] Shrirang K. Karandikar and Sachin S. Sapatnekar. Extending Logical Effort for Fast Comparisons of Circuit Implementations. SRC TECHCON, August 2003.

[ 2] Shrirang K. Karandikar. A Quick Introduction to LaTeX. Twin Cities Linux Users Group, Monthly Meeting, February 2004.

[ 3] P. Kudva, B. Curran, S. K. Karandikar, M. Mayo, S. Carey and S. S. Sapatnekar. Early Performance Prediction. In Workshop on Complexity-Effective Design, 2005.

[ 4] Shrirang K. Karandikar, Charles J. Alpert, Mehmet C. Yildiz, Paul G. Villarrubia, Stephen T. Quay and Tuhin Mahmud. Fast Electrical Correction Using Resizing and Buffering. In International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems, 2006

[ 5] Shiyan Hu, Charles J. Alpert, Jiang Hu, Shrirang K. Karandikar, Zhuo Li, Weiping Shi and Chin-Ngai Sze. Fast Algorithms for Slew Constrained Minimum Cost Buffering. In 7th International Austin CAS Conference, 2006

[ 6] C. J. Alpert, S. K. Karandikar et al. The Mercury Flow -- Integrating PLATO into High-Effort PDS. In IBM Design Automation Workshop, 2006.

[ 7] Shrirang K. Karandikar, Chin-Ngai Sze et al. EVE -- Electrical Violation Eliminator. In IBM Design Automation Workshop, 2006.

[ 8] Shrirang K. Karandikar, S. K. Dash and S. Rai. Regional Climate Modelling and High Performance Computation. In First Annual Workshop on Climate Modelling, 2008.

[ 9] Shrirang K. Karandikar. High Performance Computing Solutions at CRL. In ATIP First Workshop on HPC in India: Indigenous Hardware, Software, and Infrastructure Research, 2009.

[10] Shrirang K. Karandikar, Kiran Nalawade and Sandip Tikkar. Performance Optimization. In IEEE International Conference on High Performance Computing, 2009.

[11] Shrirang K. Karandikar. CRL's Experiments and Experiences with Grid and Cloud. In GARUDA-NKN Partners Meet, 2011.

[12] Shrirang K. Karandikar. From Cycles to Solutions. In International Conference on Frontiers of Computer Science, 2011.

[13] Nitin Joshi, Shashank Srivastava, Milner Kumar, Jojumon Kavalan, Shrirang K. Karandikar and Arundhati Saraph. Parallelization of Velvet, A de-novo Genmone Sequence Assembler. In IEEE International Conference on High Performance Computing, 2011.

[14] Varad R. Deshmukh and Nishchay S. Mhatre and Shrirang K. Karandikar. Techniques for Benchmarking CPU Microarchitecture for Performance Evaluation. In IEEE International Conference on High Performance Computing, 2011.

[15] Shrirang K. Karandikar. High Performance Computing and the Cloud. In Challenges in Cloud Computing, DIAT Pune, 2011.


Patents (Applied/Pending)

[1] Shrirang K. Karandikar, Charles J. Alpert, Mehmet C. Yildiz, Stephen T. Quay, Tuhin Mahmud and Paul G. Villarrubia. EVE: Electrical Violation Eliminator. IBM Invention Disclosure AUS8-2005-1486, August 2005.

[2] Charles J. Alpert, Shrirang K. Karandikar, Tuhin Mahmud, Stephen T. Quay and Chin-Ngai Sze. Slew Constrained Minimum Cost Buffering. U. S. Patent 7,448,007, issued November 2008.

[3] Charles J. Alpert, Shrirang K. Karandikar, Tuhin Mahmud, Stephen T. Quay and Chin-Ngai Sze. Slew Constrained Minimum Cost Buffering. U. S. Patent 7,890,905, issued February 2011.

[4] Zhuo Li, Charles J. Alpert, Cliff Sze, and Shrirang K. Karandikar. Placement Congestion Driven Node Cost Model for Buffer Insertion. IBM Invention Disclosure AUS8-2006-1392, October 2006.

[5] David A. Papa, Charles J. Alpert, Gi-Joon Nam, Arvind K. Karandikar, Zhuo Li, Chin-Ngai Sze. A Method To Improve the Timing of A Circuit by Moving Badly Placed Gates. IBM Invention Disclosure AUS8-2007-0328, February 2007.

Most recently updated Jan 26 2010, 1330 hrs IST